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DS1678 Real-Time Event Recorder
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POWER CONTROL
The device is fully accessible and data can be written and read when VCC is greater than VPF. However,
when VCC falls below V
PF, the internal registers are blocked from any access. The device power is
switched from VCC to VBAT when VCC drops below VBAT. Operation, except for the I
2C interface, is
maintained from the VBAT source until VCC is returned to nominal levels (Table 1). After VCC returns
above VPF, read and write access is allowed.
Table 1. Power Control
SUPPLY
CONDITION
READ/WRITE
ACCESS
POWERED
BY
VCC < VPF, VCC < VBAT
No
VBAT
VCC < VPF, VCC > VBAT
No
VCC
VCC > VPF, VCC > VBAT
Yes
VCC
OSCILLATOR CIRCUIT
The DS1678 uses an external 32.768kHz crystal. The oscillator circuit does not require any external
resistors or capacitors (CL) to operate. Table 2 specifies several crystal parameters for the external crystal,
and the oscillator block in the Block Diagram shows a functional schematic of the oscillator circuit. Using
a crystal with the specified characteristics, the startup time is usually less than one second.
Table 2. Crystal Specifications*
PARAMETER SYMBOL
MIN
TYP
MAX UNITS
Nominal Frequency
fO
32.768
kHz
Series Resistance
ESR
45
k
Load Capacitance
CL
12.5
pF
*
The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to
Application Note 58: Crystal Considerations for Dallas Real-Time Clocks
for additional specifications.
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 1 shows a
typical PC board layout for crystal and oscillator isolation from noise. Refer to Application Note 58:
Crystal Considerations with Dallas Real-Time Clocks for detailed information.
Figure 1. Typical Crystal Layout
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
X1
X2
GND
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